[ Chris Fallin ]

Computer Architecture projects

• pipeproc (tar.gz): A 5-stage pipelined processor based on the six-instruction processor described in Frank Vahid's Digital Design textbook, with significant extensions. Includes full data-forwarding and stall logic, as well as support for a branch predictor. Developed as a group project for CSE 30321, Computer Architecture I, at Notre Dame in fall 2007. I wrote the pipeline core, and another group member wrote the branch predictor; I've excluded the branch predictor from this distribution (the processor still works, albeit with slightly worse performance). The core achieved an average CPI of 1.21 in our tests. The model was debugged with Modelsim (a waveform view save is included) and also with Icarus Verilog.
• JAMMER (tar.gz): Created for Computer Architecture II, CSE 30322, the following spring. JAMMER is a pipelined RISC processor with some special support for running translated stack-machine code -- namely, a unique indexed-register mode. This combines with a software trap mechanism that pages the register file through the stack in main memory. We achieved this by inserting an additional pipeline stage before register read to rewrite the register fields of the instruction. This strange beast runs translated code from the JAM3D architecture, as specified in class, which is based loosely on the Java VM. I wrote the translation firmware in about 1K lines of native JAMMER assembly, and wrote the assembler and simulator to test it. (I had written a JAM3D simulator for an earlier stage of the project and adapted its backend.) Two very capable collaborators developed the unique hardware. The firmware performs just-in-time translation: JAM3D is a 12-bit machine, and JAMMER is 16 bits wide, so the top nibble of all JAM3D code is 0. A 0-opcode in JAMMER is a trap to translation firmware. So an attempt to execute JAM3D code directly will trap to the JIT routine. The firmware writes translated code by concatenating snippets for each instruction (most translating to one or two native instructions) and then rewrites the JAM3D code segment as a series of jumps to the proper offsets. All branches in the translated code vector through the original code segment, to avoid the need to track the translation mapping directly. Again, I'm including only the pieces I wrote: the translation firmware and the simulator/assembler toolchain. This is enough to do something useful, though it does not include the actual processor core.